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KM68V1000B, KM68U1000B Family
Document Title
128K x8 bit Low Power and Low Voltage CMOS Static RAM
CMOS SRAM
Revision History
Revision No. History
0.0 1.0 2.0 Initial draft Finalize Revise - Change datasheet format
Draft Data
Remark
August 12, 1995 Preliminary April 12, 1996 March 7, 1998 Final Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
Revision 2.0 March 1998
KM68V1000B, KM68U1000B Family
128K x8 bit Low Power and Low Voltage CMOS Static RAM
FEATURES
* Process Technology : Poly Load * Organization : 128Kx8 * Power Supply Voltage : KM68V1000B family : 3.0~3.6V KM68U1000B family : 2.7~3.3V * Low Data Retention Voltage : 2V(Min) * Three state output and TTL Compatible * Package Type : 32-SOP, 32-TSOP1-0820F/R
CMOS SRAM
GENERAL DESCRIPTION
The KM68V1000B and KM68U1000B families are fabricated by SAMSUNGs advanced CMOS process technology. The families support various operating temperature ranges and have various package types for user flexibility of system design. The families also support low data retention voltage for battery back-up operation with low data retention current.
PRODUCT FAMILY
Power Dissipation Product Family KM68V1000BL/L-L KM68U1000BL/L-L KM68V1000BLE/LE-L KM68U1000BLE/LE-L KM68V1000BLI/LI-L KM68U1000BLI/LI-L Operating Temperature Vcc Range 3.0~3.6V 2.7~3.3V 3.0~3.6V 2.7~3.3V 3.0~3.6V 2.7~3.3V Speed(ns) 701)/100 100 701)/100 100 701)/100 100 Standby (ISB1, Max) 50/15A 50/15A 100/20A 50/15A 100/20A 50/15A 40mA 32-SOP 32-TSOP1- R/F Operating (ICC2, Max) PKG Type
Commercial(0~70C) Extended(-25~85C) Industrial(-40~85C)
1. The parameter is measured with 30pF test load.
PIN DESCRIPTION
A11 A9 A8 A13 WE VCC CS2 A15 A15 VCC CS2 NC A16 WE A14 A12 A13 A7 A6 A8 A5 A9 A4 A11 A4 A10 A5 A6 CS1 A7 I/O8 A12 A14 I/O7 A16 NC I/O6 A15 I/O5 VCC CS2 I/O4 A13 WE A8 A9 A11 OE 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS I/O4 I/O5 I/O6 I/O7 I/O8 CS1 A10 OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CS1 I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 A3
FUNCTIONAL BLOCK DIAGRAM
Clk gen. Precharge circuit.
N.C A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26
32-TSOP Type 1 - Forward
A4 A5 A6 A7 A12 A13 A14 A15 A16
Row select
Memory array 512 rows 256x8 columns
32-SOP
25 24 23 22 21 20 19 18 17
32-TSOP Type 1 - Reverse
I/O1 I/O8
Data cont
I/O Circuit Column select
Data cont
A0 A1 A2 A3 A8 A9 A10 A11
Name
CS1,CS2 OE WE A0~A16 I/O1~I/O8 Vcc Vss N.C
Function
Chip Select Inputs Output Enable Input Write Enable Input Address Inputs Data Inputs/Outputs Power Ground No Connection
CS1 CS2 WE OE
Control Logic
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
Revision 2.0 March 1998
KM68V1000B, KM68U1000B Family
PRODUCT LIST
Commercial Temperarure Products (0~70C) Part Name
KM68V1000BLG-7 KM68V1000BLG-10 KM68V1000BLT-7 KM68V1000BLT-10 KM68V1000BLR-7 KM68V1000BLR-10 KM68V1000BLG-7L KM68V1000BLG-10L KM68V1000BLT-7L KM68V1000BLT-10L KM68V1000BLR-7L KM68V1000BLR-10L KM68U1000BLG-10 KM68U1000BLT-10 KM68U1000BLR-10 KM68U1000BLG-10L KM68U1000BLT-10L KM68U1000BLR-10L
CMOS SRAM
Industrial Temperarure Products (-40~85C) Part Name
KM68V1000BLGI-7 KM68V1000BLGI-10 KM68V1000BLTI-7 KM68V1000BLTI-10 KM68V1000BLRI-7 KM68V1000BLRI-10 KM68V1000BLGI-7L KM68V1000BLGI-10L KM68V1000BLTI-7L KM68V1000BLTI-10L KM68V1000BLRI-7L KM68V1000BLRI-10L KM68U1000BLGI-10 KM68U1000BLTI-10 KM68U1000BLRI-10 KM68U1000BLGI-10L KM68U1000BLTI-10L KM68U1000BLRI-10L
Extended Temperarure Products (-25~85C) Part Name
KM68V1000BLGE-7 KM68V1000BLGE-10 KM68V1000BLTE-7 KM68V1000BLTE-10 KM68V1000BLRE-7 KM68V1000BLRE-10 KM68V1000BLGE-7L KM68V1000BLGE-10L KM68V1000BLTE-7L KM68V1000BLTE-10L KM68V1000BLRE-7L KM68V1000BLRE-10L KM68U1000BLGE-10 KM68U1000BLTE-10 KM68U1000BLRE-10 KM68U1000BLGE-10L KM68U1000BLTE-10L KM68U1000BLRE-10L
Function
32-SOP,70ns,3.3V,L 32-SOP,100ns,3.3V,L 32-TSOP F,70ns,3.3V,L 32-TSOP F,100ns,3.3V,L 32-TSOP R,70ns,3.3V,L 32-TSOP R,100ns,3.3V,L 32-SOP,70ns,3.3V,LL 32-SOP,100ns,3.3V,LL 32-TSOP F,70ns,3.3V,LL 32-TSOP F,100ns,3.3V,LL 32-TSOP R,70ns,3.3V,LL 32-TSOP R,100ns,3.3V,LL 32-SOP,100ns,3.0V,L 32-TSOP F,100ns,3.0V,L 32-TSOP R,100ns,3.0V,L 32-SOP,100ns,3.0V,LL 32-TSOP F,100ns,3.0V,LL 32-TSOP R,100ns,3.0V,LL
Function
32-SOP,70ns,3.3V,L 32-SOP,100ns,3.3V,L 32-TSOP F,70ns,3.3V,L 32-TSOP F,100ns,3.3V,L 32-TSOP R,70ns,3.3V,L 32-TSOP R,100ns,3.3V,L 32-SOP,70ns,3.3V,LL 32-SOP,100ns,3.3V,LL 32-TSOP F,70ns,3.3V,LL 32-TSOP F,100ns,3.3V,LL 32-TSOP R,70ns,3.3V,LL 32-TSOP R,100ns,3.3V,LL 32-SOP,100ns,3.0V,L 32-TSOP F,100ns,3.0V,L 32-TSOP R,100ns,3.0V,L 32-SOP,100ns,3.0V,LL 32-TSOP F,100ns,3.0V,LL 32-TSOP R,100ns,3.0V,LL
Function
32-SOP,70ns,3.3V,L 32-SOP,100ns,3.3V,L 32-TSOP F,70ns,3.3V,L 32-TSOP F,100ns,3.3V,L 32-TSOP R,70ns,3.3V,L 32-TSOP R,100ns,3.3V,L 32-SOP,70ns,3.3V,LL 32-SOP,100ns,3.3V,LL 32-TSOP F,70ns,3.3V,LL 32-TSOP F,100ns,3.3V,LL 32-TSOP R,70ns,3.3V,LL 32-TSOP R,100ns,3.3V,LL 32-SOP,100ns,3.0V,L 32-TSOP F,100ns,3.0V,L 32-TSOP R,100ns,3.0V,L 32-SOP,100ns,3.0V,LL 32-TSOP F,100ns,3.0V,LL 32-TSOP R,100ns,3.0V,LL
FUNCTIONAL DESCRIPTION
CS1 H X1) L L L CS2 X
1)
OE X
1)
WE X
1)
I/O Pin High-Z High-Z High-Z Dout Din
Mode Deselected Deselected Output Disabled Read Write
Power Standby Standby Active Active Active
L H H H
X1) H L X1)
X1) H H L
1. X means dont care(Must be in high or low status.)
ABSOLUTE MAXIMUM RATINGS1)
Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Symbol VIN,VOU VCC PD TSTG TA Ratings -0.5 to VCC+0.5 -0.3 to 4.6 0.7 -65 to 150 0 to 70 -25 to 85 -40 to 85 Soldering temperature and time TSOLDER 260C, 10sec (Lead Only) Unit V V W C C C C Remark KM68V1000BL, KM68U1000BL KM68V1000BLE, KM68U1000BLE KM68V1000BLI, KM68U1000BLI -
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Revision 2.0 March 1998
KM68V1000B, KM68U1000B Family
RECOMMENDED DC OPERATING CONDITIONS1)
Item Supply voltage Ground Input high voltage Input low voltage Symbol Vcc Vss VIH VIL Product KM68V1000B Family KM68U1000B Family All Family KM68V1000B, KM68U1000B Family KM68V1000B, KM68U1000B Family Min 3.0 2.7 0 2.2 -0.33) Typ 3.3 3.0 0 -
CMOS SRAM
Max 3.6 3.3 0 Vcc+0.32) 0.4 Unit V V V V
Note: 1. Commercial Product : TA=0 to 70C, unless otherwise specified Extended Product : TA=-25 to 85C, unless otherwise specified Industrial Product : TA=-40 to 85C, unless otherwise specified 2. Overshoot : VCC+3.0V in case of pulse width30ns 3. Undershoot : -3.0V in case of pulse width30ns 4. Overshoot and undershoot are sampled, not 100% tested
CAPACITANCE1) (f=1MHz, TA=25C)
Item Input capacitance Input/Output capacitance
1. Capacitance is sampled not, 100% tested
Symbol CIN CIO
Test Condition VIN=0V VIO=0V
Min -
Max 6 8
Unit pF pF
DC AND OPERATING CHARACTERISTICS
Item Input leakage current Output leakage current Operating power supply current Average operating current Symbol ILI ILO ICC ICC1 ICC2 Output low voltage Output high voltage Standby Current(TTL) KM68V1000BL/L-L KM68V1000BLE/LE-L KM68V1000BLI/LI-L ISB1 KM68U1000BL/L-L KM68U1000BLE/LE-L KM68U1000BLI/LI-L VOL VOH ISB VIN=Vss to Vcc CS1=VIH or CS2=VIL or WE=VIL, Vio=Vss to Vcc CS1=VIL,CS2=VIH,VIN=VIH or VIL, IIO=0mA Cycle time=1s, 100% duty, IIO=0mA, CS10.2V, CS2VCC-0.2V, VIN0.2V or VINVCC-0.2V Min cycle, 100% duty, IIO=0mA, CS1=VIL, CS2=VIH IOL=2.1mA IOH=-1.0mA CS1=VIH, CS2=VIL Low Power Low Low Power Low Power Low Low Power Low Power Low Low Power Low Power Low Low Power Test Conditions Min -1 -1 2.2 Typ 2 3 30 1.0 0.5 1.0 0.5 1.0 0.5 1.0 0.5 Max 1 1 5 5 40 0.4 0.3 50 15 100 20 50 15 50 15 Unit A A mA mA mA V V mA A A A A
Standby Current (CMOS)
CS1Vcc-0.2V CS2Vcc-0.2V or CS20.2V Other input =0~Vcc
Revision 2.0 March 1998
KM68V1000B, KM68U1000B Family
AC OPERATING CONDITIONS
TEST CONDITIONS( Test Load and Input/Output Reference)
Input pulse level : 0.4 to 2.2V Input rising and falling time : 5ns Input and output reference voltage :1.5V Output load(see right) : CL=100pF+1TTL CL=30pF+1TTL CL1)
CMOS SRAM
1. Including scope and jig capacitance
AC CHARACTERISTICS
(Commercial product :TA=0 to 70C, Extended product :TA=-25 to 85C, Industrial product : TA=-40 to 85C KM68V1000B Family:Vcc=3.0~3.6V, KM68U1000B Family:Vcc=2.7~3.3V)
Speed Bins Parameter List Symbol Min Read cycle time Address access time Chip select to output Output enable to valid output Read Chip select to low-Z output Output enable to low-Z output Chip disable to high-Z output Output disable to high-Z output Output hold from address change Write cycle time Chip select to end of write Address set-up time Address valid to end of write Write Write pulse width Write recovery time Write to output high-Z Data to write time overlap Data hold from write time End write to output low-Z tRC tAA tCO tOE tLZ tOLZ tHZ tOHZ tOH tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW 70 10 5 0 0 10 70 60 0 60 55 0 0 30 0 5 70ns Max 70 70 35 25 25 25 Min 100 10 5 0 0 15 100 80 0 80 70 0 0 40 0 5 100ns Max 100 100 50 30 30 30 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units
DATA RETENTION CHARACTERISTICS
Item Vcc for data retention VDR KM68V1000BL/L-L KM68V1000BLE/LE-L KM68V1000BLI/LI-L Data retention current IDR KM68U1000BL/L-L KM68U1000BLE/LE-L KM68U1000BLI/LI-L Data retention set-up time Recovery time tSDR tRDR Vcc=3.0V CS1Vcc-0.2V CS2Vcc-0.2V or CS20.2V Symbol
1)
Test Condition CS1 Vcc-0.2V Low Power Low Low Power Low Power Low Low Power Low Power Low Low Power Low Power Low Low Power See data retention waveform
Min 2.0 0 5
Typ 1 0.5 -
Max 3.6 30 15 50 20 25 10 25 15 -
Unit V
A
ms
1. CSVCC-0.2V, CS2VCC-0.2V(CS1 controlled) or CS20.2V(CS2 controlled)
Revision 2.0 March 1998
KM68V1000B, KM68U1000B Family
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VlL, WE=VIH)
tRC Address tOH Data Out Previous Data Valid tAA
CMOS SRAM
Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC Address tAA tCO1 CS1 tHZ(1,2) CS2 tCO2 tOE tOH
OE tOLZ tLZ Data Valid tOHZ
Data out
NOTES (READ CYCLE)
High-Z
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection.
Revision 2.0 March 1998
KM68V1000B, KM68U1000B Family
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC Address tCW(2) CS1 tAW CS2 tCW(2) tWP(1) WE tAS(3) Data in tWHZ Data out Data Undefined tDW Data Valid tOW tDH tWR(4)
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1
Controlled)
tWC Address tAS(3) CS1 tAW CS2 tWP(1) WE tDW Data in Data Valid tDH tCW(2) tWR(4)
Data out
High-Z
High-Z
Revision 2.0 March 1998
KM68V1000B, KM68U1000B Family
TIMING WAVEFORM OF WRITE CYCLE(3) (CS1 Controlled)
tWC Address tAS(3) CS1 tAW CS2 tCW(2) tWP(1) tDW Data in Data Valid tDH tCW(2) tWR(4)
CMOS SRAM
WE
Data out
NOTES (WRITE CYCLE)
High-Z
High-Z
1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low, CS2 going high and WE going low : A write end at the earliest transition among CS1 going high, CS2 going low and WE going high, tWP is measured from the begining of write to the end of write. 2. tCW is measured from the CS1 going low or CS2 going high to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR(1) applied in case a write ends as CS1 or WE going high tWR(2) applied in case a write ends as CS2 going to low.
DATA RETENTION WAVE FORM
CS1 controlled
VCC 3.0/2.7V1) tSDR Data Retention Mode tRDR
2.2V VDR CS1VCC - 0.2V CS1 GND
CS2 controlled
VCC 3.0/2.7V1) CS2 tSDR
Data Retention Mode
tRDR
VDR 0.4V GND
1. 3.0V for KM68V1000B Family , 2.7V for KM68U1000B Family
CS20.2V
Revision 2.0 March 1998
KM68V1000B, KM68U1000B Family
PACKAGE DIMENSIONS
32 PIN PLASTIC SMALL OUTLINE PACKAGE (525mil)
CMOS SRAM
Units : millimeter(inch)
0~8 #32 #17
14.120.30 0.5560.012
11.430.20 0.4500.008
#1 20.87 0.822 MAX 20.470.20 0.8060.008
#16 2.740.20 0.1080.008 3.00 0.118 MAX
13.34 0.525
0.20 +0.10 -0.05 0.008+0.004 -0.002
0.800.20 0.0310.008
0.10 MAX 0.004 MAX
+0.100 -0.050 +0.004 0.016 -0.002
(
0.71 ) 0.028
0.41
1.27 0.050
0.05 0.002 MIN
Revision 2.0 March 1998
KM68V1000B, KM68U1000B Family
PACKAGE DIMENSIONS
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820F)
CMOS SRAM
Units : millimeter(inch)
0.20
+0.10 -0.05 0.008+0.004 -0.002
20.000.20 0.7870.008 #32 ( 8.40 0.331 MAX 8.00 0.315 0.25 ) 0.010
#1
0.50 0.0197
#16
#17 1.000.10 0.0390.004 1.20 0.047 MAX
+0.10 -0.05 0.006+0.004 -0.002
0.05 0.002 MIN
0.25 0.010 TYP
18.400.10 0.7240.004
0.15
0~8
0.45 ~0.75 0.018 ~0.030
(
0.50 ) 0.020
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820R)
0.20
+0.10 -0.05 0.008+0.004 -0.002
20.000.20 0.7870.008 #17 ( 8.40 0.331 MAX 8.00 0.315 0.25 ) 0.010
#16
0.50 0.0197
#1
#32 1.000.10 0.0390.004 1.20 0.047 MAX 0.05 0.002 MIN
0.25 0.010 TYP
18.400.10 0.7240.004
0~8
0.45 ~0.75 0.018 ~0.030
(
0.50 ) 0.020
0.10 MAX 0.004 MAX
+0.10 -0.05 +0.004 0.006 -0.002
0.15
Revision 2.0 March 1998
0.10MAX 0.004MAX

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